The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2015

Filed:

Jul. 31, 2012
Applicants:

Changliang Qin, Beijing, CN;

Peizhen Hong, Beijing, CN;

Huaxiang Yin, Beijing, CN;

Inventors:

Changliang Qin, Beijing, CN;

Peizhen Hong, Beijing, CN;

Huaxiang Yin, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/36 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 21/306 (2006.01); H01L 29/66 (2006.01); H01L 21/3065 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 21/30604 (2013.01); H01L 21/30608 (2013.01); H01L 21/3065 (2013.01); H01L 29/66477 (2013.01); H01L 21/26506 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form Σ-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the Σ-shaped source/drain grooves.


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