The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

Mar. 07, 2014
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Mark Jensen, Pittsburgh, PA (US);

Andrew Goodrich, Campbell, CA (US);

Valery Fouron, Pittsburgh, PA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/505 (2013.01); G06F 2217/84 (2013.01);
Abstract

Technology for synthesizing a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the circuit's behavior, or other functionality, via multiple statements, including a conditional statement. The technology includes analyzing statements upstream and/or downstream from the conditional statement, identifying one or more statements having dependency relationships with the conditional statement and inferring one or more potential clock domains for logic associated with the identified statements.


Find Patent Forward Citations

Jensen, Mark. (2015). Synthesis of clock gated circuit (U.S. Patent No. 9003339). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9003339

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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