The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

Sep. 25, 2012
Applicants:

Qiong Cai, Barcelona, ES;

Nevin Hyuseinova, Barcelona, ES;

Serkan Ozdemir, Barcelona, ES;

Ferad Zyulkyarov, Barcelona, ES;

Marios Nicolaides, Barcelona, ES;

Blas Cuesta, Barcelona, ES;

Inventors:

Qiong Cai, Barcelona, ES;

Nevin Hyuseinova, Barcelona, ES;

Serkan Ozdemir, Barcelona, ES;

Ferad Zyulkyarov, Barcelona, ES;

Marios Nicolaides, Barcelona, ES;

Blas Cuesta, Barcelona, ES;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/12 (2006.01);
U.S. Cl.
CPC ...
G06F 12/126 (2013.01);
Abstract

Techniques and mechanisms for adaptively changing between replacement policies for selecting lines of a cache for eviction. In an embodiment, evaluation logic determines a value of a performance metric which is for writes to a non-volatile memory. Based on the determined value of the performance metric, a parameter value of a replacement policy is determined. In another embodiment, cache replacement logic performs a selection of a line of cache for data eviction, where the selection is in response to the policy unit providing an indication of the determined parameter value.


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