The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

Nov. 12, 2012
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Wyeman Chen, Fremont, CA (US);

Michael Nikkhoo, San Jose, CA (US);

Amir Salehi, San Jose, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 7/10 (2006.01); H01R 12/00 (2006.01); H05K 1/11 (2006.01); H05K 13/04 (2006.01); H01R 12/52 (2011.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H01R 9/095 (2013.01); H05K 13/0465 (2013.01); Y10T 29/49144 (2015.01); H01R 12/526 (2013.01); H05K 1/111 (2013.01); H05K 3/3415 (2013.01); H05K 2201/09427 (2013.01); H05K 2201/09709 (2013.01); H05K 2203/1572 (2013.01); H05K 2203/304 (2013.01);
Abstract

Electronic devices may be provided with printed circuits to which integrated circuits and other electrical components may be mounted. A first printed circuit may have a first surface with an array of contact pads arranged in rows and columns. Each column of contact pads may have a series of contact pads separated by gaps. The contact pads in each column may be staggered with respect to the contact pads in adjacent columns such that each contact pad in a given column is horizontally adjacent to associated gaps in the adjacent columns. A component may be mounted to an opposing surface of the printed circuit such that it overlaps one of the gaps between the staggered contact pads. By mounting the component to portions of the first printed circuit that do not overlap the staggered contact pads, the risk of damaging the electrical component during solder reflow operations may be minimized.


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