The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2015
Filed:
Jul. 30, 2012
Chi Shun Lo, San Diego, CA (US);
Je-hsiung Jeffrey Lan, San Diego, CA (US);
Mario Francisco Velez, San Diego, CA (US);
Robert Paul Mikulka, Oceanside, CA (US);
Chengjie Zuo, Santee, CA (US);
Changhan Hobie Yun, San Diego, CA (US);
Jonghae Kim, Surabaya, CA (US);
Chi Shun Lo, San Diego, CA (US);
Je-Hsiung Jeffrey Lan, San Diego, CA (US);
Mario Francisco Velez, San Diego, CA (US);
Robert Paul Mikulka, Oceanside, CA (US);
Chengjie Zuo, Santee, CA (US);
Changhan Hobie Yun, San Diego, CA (US);
Jonghae Kim, Surabaya, CA (US);
QUALCOMM MEMS Technologies, Inc., San Diego, CA (US);
Abstract
This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile