The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

Jan. 28, 2014
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventor:

Adrian Luigi Leuciuc, Frederick, MD (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/08 (2006.01); H03M 1/12 (2006.01); H03M 1/10 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1023 (2013.01); H03M 1/121 (2013.01); H03M 1/0836 (2013.01);
Abstract

A system and method are provided for adaptive self-calibration to remove sample timing error in time-interleaved ADC of an analog signal. A plurality of ADC channels recursively sample the analog signal within a series of sample segments according to a predetermined sampling clock to generate a time-interleaved series of output samples. A timing skew detection unit is coupled to the ADC channels, which generates for each sample segment a timing skew factor indicative of sampling clock misalignment within the sample segment. Each timing skew factor is generated based adaptively on the output samples for a selective combination of segments including at least one preceding and at least one succeeding sample segment. A plurality of timing control units respectively coupled to the ADC channels adjust time delays for the sampling clock within respective sample segments responsive to the timing skew factors, thereby substantially aligning the sample segments with the sampling clock.


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