The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2015
Filed:
Sep. 30, 2011
Applicants:
Guido Droege, Braunschweig, DE;
Niklas Linkewitsch, Evessen, DE;
Andre Schaefer, Braunschweig, DE;
Inventors:
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/522 (2006.01); H01L 25/065 (2006.01); H01L 23/64 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 25/0657 (2013.01); H01L 23/642 (2013.01); H01L 23/481 (2013.01); H01L 2223/6622 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06544 (2013.01); H01L 2224/16145 (2013.01);
Abstract
Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.
Droege, Guido. (2015). Interlayer communications for 3d integrated circuit stack (U.S. Patent No. 9000577). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9000577
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile