The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

Feb. 23, 2012
Applicants:

Ki-hong Lee, Gyeonggi-do, KR;

Kwon Hong, Gyeonggi-do, KR;

Dae-gyu Shin, Gyeonggi-do, KR;

Inventors:

Ki-Hong Lee, Gyeonggi-do, KR;

Kwon Hong, Gyeonggi-do, KR;

Dae-Gyu Shin, Gyeonggi-do, KR;

Assignee:

Hynix Semiconductor Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 29/78 (2006.01); H01L 29/772 (2006.01); H01L 21/28 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28282 (2013.01); H01L 27/11582 (2013.01); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01);
Abstract

A nonvolatile memory device includes a pipe gate having a pipe channel hole; a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked over the pipe gate; a pair of columnar cell channels passing through the interlayer insulation layers and the gate electrodes and coupling a pipe channel formed in the pile channel hole; a first blocking layer and a charge trapping and charge storage layer formed on sidewalls of the columnar cell channels; and a second blocking layer formed between the first blocking layer and the plurality of gate electrodes.


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