The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2015
Filed:
Nov. 21, 2013
Korea Advanced Nano Fab Center, Suwon, Gyeonggi-Do, KR;
Sungkyunkwan University Research & Business Foundation, Suwon, Gyeonggi-Do, KR;
Won Kyu Park, Seoul, KR;
Jong Gon Heo, Gyeonggi-Do, KR;
Dong Hwan Jun, Gyeonggi-Do, KR;
Jin Hong Park, Gyeonggi-Do, KR;
Jae Woo Shim, Gyeonggi-Do, KR;
Korea Advanced Nano Fab Center, Suwon, Gyeonggi-Do, KR;
Sungkyunkwan University Research & Business Foundation, Suwon, Gyeonggi-Do, KR;
Abstract
This invention relates to a method of healing defects at junctions of a semiconductor device, which includes growing a p-Ge layer on a substrate, performing ion implantation on the p-Ge layer to form an n+ Ge region or performing in-situ doping on the p-Ge layer and then etching to form an n+ Ge region or depositing an oxide film on the p-Ge layer and performing patterning, etching and in-situ doping to form an n+ Ge layer, forming a capping oxide film, performing annealing at 600˜700° C. for 1˜3 hr, and depositing an electrode, and in which annealing enables Ge defects at n+/p junctions to be healed and the depth of junctions to be comparatively reduced, thus minimizing leakage current, thereby improving properties of the semiconductor device and achieving high integration and fineness of the semiconductor device.