The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2015

Filed:

Nov. 14, 2014
Applicant:

Powerchip Technology Corporation, Hsinchu, TW;

Inventors:

Chan-Ching Lin, Taipei, TW;

Chen-Hao Huang, Miaoli County, TW;

Tzung-Bin Huang, Hsinchu, TW;

Chun-Cheng Chen, Changhua County, TW;

Ching-Hua Chen, Hsinchu, TW;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 45/02 (2006.01); H01L 21/02 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1608 (2013.01); H01L 45/1253 (2013.01); H01L 27/2463 (2013.01); H01L 29/6609 (2013.01);
Abstract

A method of fabricating a resistive random access memory (RRAM) device is disclosed. A plurality of word lines extending along a first direction are formed on a substrate with a recess between the word lines. A spacer-type resistance layer and a top electrode layer are formed on a sidewall of each of the word lines. A photoresist stripe pattern extending along a second direction is then formed on the substrate. The first direction is perpendicular to the second direction. An etching process is performed to remove the top electrode layer and the spacer-type resistance layer not covered by the photoresist stripe pattern to form a plurality of top electrodes. A diode is formed on each of the top electrodes.


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