The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2015
Filed:
Dec. 20, 2012
Stmicroelectronics Pvt. Ltd., Greater Noida, IN;
Stmicroelectronics S.r.i., Agrate Brianza, IT;
Nicolas Bernard Grossier, Oreno di Vimercate, IT;
Sabyasachi Das, Noida, IN;
V Srinivasan, Greater Noida, IN;
STMicroelectronics S.R.L., Agrate Brianza (MB), IT;
STMicroelectronics International N.V., Amsterdam, NL;
Abstract
A Voltage regulator includes a first input terminal configured to receive an input supply voltage, includes a second input terminal configured to receive a regulated output supply voltage as a function of the input supply voltage or to receive a test supply voltage and comprises a power transistor including an input terminal configured to receive the input supply voltage and including an output terminal configured to generate the regulated output supply voltage. The Voltage regulator is configured, during a start-up phase of a test operation mode, to receive a control signal equal to the input supply voltage, is configured to receive the input supply voltage having a substantially increasing trend, detect that the input supply voltage is equal to a first voltage threshold and generate, as a function of the detected signal and of the control signal, a by-pass signal having a transition from a first logic value to a second logic value for indicating a by-pass status of the Voltage regulator, and is configured to receive the by-pass signal having the second logic value and open the power transistor. The second input terminal is configured, during the test operation mode, to receive the test supply voltage having a test value different from a nominal value of the regulated output supply voltage.