The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2015
Filed:
Mar. 26, 2012
Hsiang-ming Chou, Hsinchu, TW;
Kuo-liang Pan, Changhua County, TW;
Chien-feng Tseng, Hsinchu County, TW;
Yi-chiu Tsai, Tainan, TW;
Chien-shao Tang, Hsinchu, TW;
Hsin-han Chen, Tainan, TW;
Hsiang-Ming Chou, Hsinchu, TW;
Kuo-Liang Pan, Changhua County, TW;
Chien-Feng Tseng, Hsinchu County, TW;
Yi-Chiu Tsai, Tainan, TW;
Chien-Shao Tang, Hsinchu, TW;
Hsin-Han Chen, Tainan, TW;
Elite Semiconductor Memory Technology Inc., Hsinchu Science Park, Hsinchu, TW;
Abstract
There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.