The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2015

Filed:

Jul. 19, 2012
Applicant:

Chao-min Wang, Hsinchu, TW;

Inventor:

Chao-Min Wang, Hsinchu, TW;

Assignee:

Subtron Technology Co., Ltd., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01); H05K 3/24 (2006.01); H05K 3/46 (2006.01); H05K 3/10 (2006.01);
U.S. Cl.
CPC ...
H05K 3/244 (2013.01); H05K 2203/1572 (2013.01); H05K 3/108 (2013.01); H05K 3/4652 (2013.01); H05K 2203/0361 (2013.01); H05K 2203/0574 (2013.01); H05K 2203/1461 (2013.01);
Abstract

A circuit board structure includes a core circuit structure, a first and a second dielectric layers, a first and a second conductive blind via structures, a third and a fourth patterned circuit layers, and a first and a second surface passivation layers. The first and the second dielectric layers have at least one first and second blind vias exposing parts of a first and a second patterned circuit layers of the core circuit structure, respectively. The first and the second conductive blind via structures are disposed into the first and the second blind vias respectively. The third and the fourth patterned circuit layers are electrically connected to the first and the second patterned circuit layers through the first and the second conductive blind via structures respectively. The first and the second surface passivation layers respectively expose parts of the third and the fourth patterned circuit layers.


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