The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2015
Filed:
May. 02, 2008
Applicants:
King W. Chan, Los Altos, CA (US);
William C. T. Shu, Palo Alto, CA (US);
Sinan Kaptanoglu, Belmont, CA (US);
Chi Fung Cheng, San Jose, CA (US);
Inventors:
King W. Chan, Los Altos, CA (US);
William C. T. Shu, Palo Alto, CA (US);
Sinan Kaptanoglu, Belmont, CA (US);
Chi Fung Cheng, San Jose, CA (US);
Assignee:
Microsemi SoC Corporation, San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H03K 19/177 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
H03K 19/177 (2013.01); G06F 15/7867 (2013.01);
Abstract
An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.