The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Apr. 11, 2011
Applicants:

Robert M. Varnum, Beaverton, OR (US);

Aslam H. Haswarey, Portland, OR (US);

Inventors:

Robert M. Varnum, Beaverton, OR (US);

Aslam H. Haswarey, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/177 (2006.01); G06F 9/00 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 15/7871 (2013.01);
Abstract

An apparatus comprising programmable logic devices including a field programmable gate array (FPGA) is presented. In one embodiment, the apparatus also comprises a programmable read only memory (PROM) to store a firmware which includes at least a system boot code and a configuration code. The apparatus further includes a configuration agent to configure the FPGA by using the configuration code and to release the reset to the CPU after the FPGA is configured. In one embodiment, the configuration agent comprises a SPI-FPGA bridge (serial peripheral interface to FPGA configuration interface). In one embodiment, the configuration agent is operable to determine whether the FPGA is ready for configuration based at least on a status from the FPGA.


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