The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Mar. 21, 2014
Applicant:

Institute of Semiconductors, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Xuliang Zhou, Beijing, CN;

Hongyan Yu, Beijing, CN;

Shiyan Li, Beijing, CN;

Jiaoqing Pan, Beijing, CN;

Wei Wang, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3065 (2013.01);
Abstract

A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiOlayer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiOlayer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiOlayer on the nMOSFET structure; performing a CMOS process.


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