The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Sep. 04, 2013
Applicants:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Fujifilm Corporation, Tokyo, JP;

Inventors:

Hyung-Rae Lee, Hwaseong-si, KR;

Keita Kato, Shizuoka, JP;

Atsushi Nakamura, Shizuoka, JP;

Yool Kang, Yongin-si, KR;

Suk-Koo Hong, Seongnam-si, KR;

Jae-Ho Kim, Yongin-si, KR;

Dong-Jun Lee, Seoul, KR;

Si-Young Lee, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/027 (2006.01); H01L 21/8238 (2006.01); H01L 21/308 (2006.01); G03F 7/004 (2006.01); G03F 7/039 (2006.01); G03F 7/32 (2006.01); G03F 7/40 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 29/66636 (2013.01); H01L 21/0274 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823878 (2013.01); H01L 21/3083 (2013.01); G03F 7/0045 (2013.01); G03F 7/0046 (2013.01); G03F 7/0397 (2013.01); G03F 7/325 (2013.01); G03F 7/405 (2013.01); H01L 29/165 (2013.01);
Abstract

A method of fabricating a semiconductor device is disclosed comprising the steps of: providing a substrate having a first region, a second region and a plurality of gate electrodes which are formed on the first and second regions of the substrate; forming a mask film to expose the first region of the substrate while covering the second region of the substrate, such that the mask film has a negative lateral profile at a boundary between the first and second regions of the substrate; forming sigma trenches in the first region of the substrate by etching the first region of the substrate using the mask film and the gate electrodes as a mask; and forming an epitaxial layer in each of the sigma trenches.


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