The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Sep. 17, 2013
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Jian Yu, Danbury, CT (US);

Jeffrey B. Johnson, Essex Junction, VT (US);

Zhengwen Li, Danbury, CT (US);

Chengwen Pei, Danbury, CT (US);

Michael Hargrove, Clinton Corners, NY (US);

Assignees:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 23/485 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66477 (2013.01); H01L 21/28518 (2013.01); H01L 21/76814 (2013.01); H01L 21/76831 (2013.01); H01L 23/485 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/66545 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.


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