The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2015

Filed:

Jun. 29, 2011
Applicants:

Keiichi Yui, Kanagawa, JP;

Akira Furuya, Kanagawa, JP;

Ken Nakata, Kanagawa, JP;

Takamitsu Kitamura, Kanagawa, JP;

Isao Makabe, Kanagawa, JP;

Inventors:

Keiichi Yui, Kanagawa, JP;

Akira Furuya, Kanagawa, JP;

Ken Nakata, Kanagawa, JP;

Takamitsu Kitamura, Kanagawa, JP;

Isao Makabe, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 21/02 (2006.01); C30B 25/14 (2006.01); C30B 25/18 (2006.01); C30B 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0262 (2013.01); C30B 25/14 (2013.01); C30B 25/186 (2013.01); C30B 29/403 (2013.01); H01L 21/02381 (2013.01); H01L 21/02458 (2013.01); H01L 21/02502 (2013.01); H01L 21/0254 (2013.01); H01L 21/02661 (2013.01);
Abstract

A method for fabricating a semiconductor device includes performing thermal cleaning for a surface of a silicon substrate in an atmosphere including hydrogen under a condition that a thermal cleaning temperature is higher than or equal to 700° C. and is lower than or equal to 1060° C., and a thermal cleaning time is longer than or equal to 5 minutes and is shorter than or equal to 15 minutes; forming a first AlN layer on the substrate with a first V/III source ratio, the forming of the first AlN layer including supplying an Al source to the surface of the substrate without supplying a N source, and supplying both the Al source and the N source; forming a second AlN layer on the first AlN layer with a second V/III source ratio that is greater than the first ratio; and forming a GaN-based semiconductor layer on the second AlN layer.


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