The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

Sep. 30, 2012
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kiriti Bhagavathula, El Dorado Hills, CA (US);

Chunyu Zhang, Folsom, CA (US);

Steven A. Peterson, Placerville, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 9/00 (2006.01); H04L 7/00 (2006.01); H04L 25/02 (2006.01); H04L 25/49 (2006.01); H04L 25/03 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0066 (2013.01); H04L 25/0272 (2013.01); H04L 25/0292 (2013.01); H04L 25/03878 (2013.01); H04L 25/4908 (2013.01);
Abstract

An embodiment of the invention includes a receiver with reduced error terms and incoming jitter tracking that improves jitter tolerance. An embodiment provides these benefits based on a voltage integrator that recovers data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. An embodiment provides these benefits based on a time integrator that recovers, using digital logic, data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. Other embodiments are described herein.


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