The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2015
Filed:
Oct. 22, 2009
Applicants:
Shinichi Chikaki, Kanagawa, JP;
Takahiro Nakayama, Ibaraki, JP;
Inventors:
Shinichi Chikaki, Kanagawa, JP;
Takahiro Nakayama, Ibaraki, JP;
Assignees:
Renesas Electronics Corporation, Kanagawa, JP;
Ulvac, Inc., Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/532 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53238 (2013.01); H01L 21/02337 (2013.01); H01L 21/02359 (2013.01); H01L 21/3105 (2013.01); H01L 21/7682 (2013.01); H01L 21/76825 (2013.01); H01L 21/76831 (2013.01); H01L 21/76843 (2013.01); H01L 21/76846 (2013.01); H01L 23/53223 (2013.01); H01L 23/53295 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A semiconductor device includes a first interconnect, a porous dielectric layer formed over the first interconnect, a second interconnect buried in the porous dielectric layer and electrically connected to the first interconnect, and a carbon-containing metal film that is disposed between the porous dielectric layer and the second interconnect and isolates these layers.