The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2015

Filed:

Nov. 05, 2013
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Shui-Yen Lu, Tainan, TW;

Chih-Ho Wang, Tainan, TW;

Jhen-Cyuan Li, New Taipei, TW;

Assignee:

United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/423 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/02274 (2013.01); H01L 21/0212 (2013.01); H01L 21/02167 (2013.01); H01L 21/0217 (2013.01); H01L 29/42364 (2013.01); H01L 21/845 (2013.01);
Abstract

A method of forming a semiconductor device includes the following steps. At least a fin structure is provided on a substrate and a gate structure partially overlapping the fin structure is formed. Then, a dielectric layer is formed on the substrate. Subsequently, a first etching process is performed to remove apart of the dielectric layer to form a first spacer surrounding the gate structure and a second spacer surrounding a sidewall of the fin structure, and a protective layer is formed in-situ to cover the gate structure and the first spacer. Finally, a second etching process is performed to remove a part of the protective layer and totally remove the second spacer.


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