The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2015
Filed:
Aug. 15, 2012
Sumit Arora, Ghaziabad, IN;
Oleg Levitsky, San Jose, CA (US);
Amit Kumar, Greater Noida, IN;
Sushobhit Singh, Noida, IN;
Sumit Arora, Ghaziabad, IN;
Oleg Levitsky, San Jose, CA (US);
Amit Kumar, Greater Noida, IN;
Sushobhit Singh, Noida, IN;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.