The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2015

Filed:

Jan. 22, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Manish Garg, Cary, NC (US);

Rajesh Kumar, Raleigh, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 8/10 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 8/10 (2013.01); G11C 11/412 (2013.01);
Abstract

Decoded 2-bit bitcells in memory for storing decoded bits, and related systems and methods are disclosed. In one embodiment, a decoded 2-bit bitcell containing 2state nodes is provided. Each state node includes storage node to store decoded bit. Storage node provides bit to read bitline, coupled to decoded word output. Each state node includes active decoded bit input coupled to storage node that receives decoded bit from decoded word to store in storage node in response to write wordline. State node comprised of 2−1 passive decoded bit inputs, each coupled to one of 2−1 remaining storage nodes. 2−1 passive decoded bit inputs receive 2−1 decoded bits not received by active decoded bit input. State node includes logic that receives 2−1 decoded bits. Logic retains decoded bit, provides it to passive decoded bit output. Passive decoded word output is coupled to storage node to store decoded bit in storage node.


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