The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2015
Filed:
May. 29, 2013
Stmicroelectronics SA, Montrouge, FR;
Commissariat a L'energie Atomique ET Aux Energies Alternatives, Grenoble, FR;
Dimitri Soussan, Grenoble, FR;
Sylvain Majcherczak, St. Pierre d'Allevard, FR;
Alexandre Valentian, Saint Egreve, FR;
Marc Belleville, Saint Egreve, FR;
STMicroelectronics SA, Montrouge, FR;
Commissariat a l'Energie Atomique et aux Energies Alternatives, Grenoble, FR;
Abstract
An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.