The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2015

Filed:

Jan. 30, 2014
Applicant:

Samsung Display Co., Ltd., Yongin, Gyeonggi-Do, KR;

Inventors:

Yu-Gwang Jeong, Yongin-si, KR;

Young-Wook Lee, Suwon-si, KR;

Sang-Gab Kim, Seoul, KR;

Woo-Geun Lee, Yongin-si, KR;

Min-Seok Oh, Yongin-si, KR;

Jang-Soo Kim, Yongin-si, KR;

Kap-Soo Yoon, Seoul, KR;

Shin-Il Choi, Seoul, KR;

Hong-Kee Chin, Suwon-si, KR;

Seung-Ha Choi, Siheung-si, KR;

Seung-Hwan Shim, Seongnam-si, KR;

Sung-Hoon Yang, Seoul, KR;

Ki-Hun Jeong, Cheongan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/44 (2010.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1259 (2013.01); H01L 27/1214 (2013.01); H01L 29/66765 (2013.01); H01L 27/1288 (2013.01);
Abstract

Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.


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