The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2015
Filed:
Aug. 06, 2010
Krishnan Srinivasan, San Jose, CA (US);
Ruben Khazhakyan, Yerevan, AM;
Harutyan Aslanyan, Yerevan, AM;
Drew E. Wingard, Palo Alto, CA (US);
Chien-chun Chou, Saratoga, CA (US);
Krishnan Srinivasan, San Jose, CA (US);
Ruben Khazhakyan, Yerevan, AM;
Harutyan Aslanyan, Yerevan, AM;
Drew E. Wingard, Palo Alto, CA (US);
Chien-Chun Chou, Saratoga, CA (US);
Sonics, Inc., Milpitas, CA (US);
Abstract
A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.