The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2015
Filed:
Aug. 30, 2011
Applicants:
Volker Strutz, Tegernheim, DE;
Stefan Landau, Wehrheim, DE;
Udo Ausserlechner, Villach, AT;
Inventors:
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/22 (2006.01); H01L 23/04 (2006.01); H01L 23/48 (2006.01); H01L 25/16 (2006.01); H01L 43/04 (2006.01); G01R 33/07 (2006.01); G01R 33/00 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/04 (2013.01); H01L 23/48 (2013.01); H01L 25/16 (2013.01); H01L 43/04 (2013.01); G01R 33/07 (2013.01); G01R 33/0047 (2013.01); H01L 24/18 (2013.01); H01L 23/3121 (2013.01); H01L 23/3171 (2013.01);
Abstract
A semiconductor chip package and a method to manufacture a semiconductor chip package are disclosed. An embodiment of the present invention comprises a substrate and a semiconductor chip disposed on the substrate and laterally surrounded by a packaging material. The package further comprises a current rail adjacent the semiconductor chip, the current rail isolated from the semiconductor chip by an isolation layer, a first external pad, and a via contact contacting the current rail with the first external pad.