The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2015

Filed:

Jul. 02, 2010
Applicant:

Shinichiro Takatani, Tao Yuan Shien, TW;

Inventor:

Shinichiro Takatani, Tao Yuan Shien, TW;

Assignee:

Win Semiconductors Corp., Tao Yuan Shien, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/778 (2006.01); H01L 21/768 (2006.01); H01L 29/423 (2006.01); H01L 29/20 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7785 (2013.01); H01L 21/76895 (2013.01); H01L 29/2003 (2013.01); H01L 29/41758 (2013.01); H01L 29/42316 (2013.01); H01L 29/7786 (2013.01);
Abstract

A multi-gate semiconductor device with inter-gate conductive regions being connected to balance resistors is provided. The multi-gate semiconductor device comprises a substrate, a multilayer structure formed upon the substrate, a first ohmic electrode, a second ohmic electrode, a plural of gate electrodes, at least one conductive region, and at least one resistive component. When put into practice, the multi-gate semiconductor device is advantageous in reducing the voltage drop along the conductive region with a minimal change in device layout, improving the OFF-state linearity while retaining a low insertion loss, and minimizing the area occupied by the resistor and hence the total chip size.


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