The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2015

Filed:

Oct. 24, 2013
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Hideomi Suzawa, Atsugi, JP;

Shinya Sasagawa, Chigasaki, JP;

Akihiro Ishizuka, Sagamihara, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66969 (2013.01); H01L 27/1214 (2013.01); H01L 27/1225 (2013.01); H01L 29/66742 (2013.01); H01L 29/7869 (2013.01); H01L 21/44 (2013.01); H01L 27/1288 (2013.01);
Abstract

Described is a method for manufacturing a semiconductor device. A mask is formed over an insulating film and the mask is reduced in size. An insulating film having a projection is formed using the mask reduced in size, and a transistor whose channel length is reduced is formed using the insulating film having a projection. Further, in manufacturing the transistor, a planarization process is performed on a surface of a gate insulating film which overlaps with a top surface of a fine projection. Thus, the transistor can operate at high speed and the reliability can be improved. In addition, the insulating film is processed into a shape having a projection, whereby a source electrode and a drain electrode can be formed in a self-aligned manner.


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