The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2015

Filed:

Jun. 23, 2011
Applicants:

Tomoyuki Ikeda, Ibi-gun, JP;

Naoaki Fujii, Ibi-gun, JP;

Seiji Izawa, Ibi-gun, JP;

Inventors:

Tomoyuki Ikeda, Ibi-gun, JP;

Naoaki Fujii, Ibi-gun, JP;

Seiji Izawa, Ibi-gun, JP;

Assignee:

Ibiden Co., Ltd., Ogaki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H05K 3/46 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H05K 3/4602 (2013.01); H01L 2224/16 (2013.01); H01L 2924/01004 (2013.01); H01L 2924/01046 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/15174 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15312 (2013.01); H01L 2924/3011 (2013.01); H05K 1/112 (2013.01); H05K 1/115 (2013.01); H05K 3/4652 (2013.01); H05K 2201/0394 (2013.01); H05K 2201/096 (2013.01); H05K 2201/09781 (2013.01); H05K 2201/10674 (2013.01); H05K 2203/0733 (2013.01); H01L 2924/01019 (2013.01); H01L 2224/16225 (2013.01);
Abstract

A method of manufacturing a multilayered printed wiring board including forming a multilayered core substrate including insulation layers and one or more stacked via structures formed through the insulation layers, the stacked via structure including vias formed in the insulation layers, respectively, the insulation layers in the multilayered core substrate including at least three insulation layers and each of the insulation layers in the multilayered core substrate including a core material impregnated with a resin, and forming a build-up structure over the multilayered core substrate and including interlaminar insulation layers and conductor circuits, each of the interlaminar insulation layers including a resin material without a core material.


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