The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2015

Filed:

Mar. 15, 2013
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Inventors:

Hiroshi Uemura, Yokohama, JP;

Hideto Furuyama, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/12 (2006.01); G02B 6/13 (2006.01); G02B 6/42 (2006.01); G02B 6/43 (2006.01);
U.S. Cl.
CPC ...
G02B 6/12 (2013.01); G02B 6/13 (2013.01); G02B 6/428 (2013.01); G02B 6/4245 (2013.01); G02B 6/43 (2013.01); G02B 6/4246 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01);
Abstract

According to one embodiment, there is provided an optoelectronic integrated package module including a silicon interposer, an optical semiconductor element formed in the silicon interposer, and a semiconductor integrated circuit chip module including a first semiconductor integrated circuit chip including a logic circuit and mounted on a first principal surface and a second semiconductor integrated circuit chip having a second principal surface side mounted on the silicon interposer. The first and second semiconductor integrated circuit chips are electrically connected to each other via the via interconnections formed inside the second semiconductor integrated circuit chip from the first principal surface. The first or second semiconductor integrated circuit chip receives an electrical signal obtained via the via interconnection by means of the unterminated reception circuit.


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