The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2015
Filed:
Sep. 30, 2011
Harmeet Sobti, Portland, OR (US);
Timothy K. Mcguire, Beaverton, OR (US);
David L. Snyder, Beaverton, OR (US);
Scott J. Alberhasky, Portland, OR (US);
Harmeet Sobti, Portland, OR (US);
Timothy K. McGuire, Beaverton, OR (US);
David L. Snyder, Beaverton, OR (US);
Scott J. Alberhasky, Portland, OR (US);
Maxim Integrated Products, Inc., San Jose, CA (US);
Abstract
Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance.