The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2015
Filed:
Apr. 25, 2012
Applicants:
Werner Juengling, Boise, ID (US);
Howard C. Kirsch, Eagle, ID (US);
Inventors:
Werner Juengling, Boise, ID (US);
Howard C. Kirsch, Eagle, ID (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/108 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10823 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 27/10826 (2013.01); H01L 27/10876 (2013.01); H01L 27/10879 (2013.01); H01L 27/10891 (2013.01); H01L 29/1037 (2013.01); H01L 29/4236 (2013.01); H01L 29/66484 (2013.01); H01L 29/66787 (2013.01); H01L 29/7855 (2013.01);
Abstract
A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.