The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2015

Filed:

Nov. 09, 2011
Applicants:

Mohan R. Nagar, Cupertino, CA (US);

Kuo-chuan Liu, Fremont, CA (US);

Mudasir Ahmad, San Jose, CA (US);

Bangalore J. Shanker, Fremont, CA (US);

Jie Xue, Dublin, CA (US);

Inventors:

Mohan R. Nagar, Cupertino, CA (US);

Kuo-Chuan Liu, Fremont, CA (US);

Mudasir Ahmad, San Jose, CA (US);

Bangalore J. Shanker, Fremont, CA (US);

Jie Xue, Dublin, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 7/06 (2006.01); H05K 3/30 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H05K 3/305 (2013.01); H01L 21/563 (2013.01); H01L 2224/73203 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H05K 2201/09036 (2013.01); H05K 2201/10674 (2013.01); H05K 2201/10977 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/10253 (2013.01);
Abstract

A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.


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