The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2015
Filed:
Nov. 08, 2011
Takaharu Oyama, Tokyo, JP;
Chiaki Matsutori, Tokyo, JP;
Tsuyoshi Nagashima, Tokyo, JP;
Shuichi Inoue, Tokyo, JP;
Hiroyuki Shida, Saitama, JP;
Hiroki Yamagishi, Saitama, JP;
Kazumasa Onuki, Saitama, JP;
Takaharu Oyama, Tokyo, JP;
Chiaki Matsutori, Tokyo, JP;
Tsuyoshi Nagashima, Tokyo, JP;
Shuichi Inoue, Tokyo, JP;
Hiroyuki Shida, Saitama, JP;
Hiroki Yamagishi, Saitama, JP;
Kazumasa Onuki, Saitama, JP;
Miraial Co., Ltd., Tokyo, JP;
Shin-Etsu Polymer Co., Ltd., Tokyo, JP;
Abstract
Wafer support shelves () are each provided with wafer support projections (A, B, B) on which parts of the outer margins of a semiconductor wafer (W) are to be placed. In each case, one of the support projections (A, B, B) is provided on the far side of the center position of the semiconductor wafer (W), and two of the support projections are provided on the near side of the center of the semiconductor wafer. By means of this structure, in a state in which a lid body () is not attached to a wafer extraction/insertion opening (), the flexure amount of the semiconductor wafers placed on the support projections of multiple locations in the wafer support shelves can be reduced with a minimal number of projections, so that a hindrance is not created to an operation such as extraction by a robot arm.