The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2015

Filed:

May. 29, 2012
Applicants:

Te-hsun Hsu, Hsinchu County, TW;

Wei-ren Chen, Pingtung County, TW;

Wen-hao Ching, Hsinchu County, TW;

Wen-chuan Chang, Taipei, TW;

Inventors:

Te-Hsun Hsu, Hsinchu County, TW;

Wei-Ren Chen, Pingtung County, TW;

Wen-Hao Ching, Hsinchu County, TW;

Wen-Chuan Chang, Taipei, TW;

Assignee:

eMemory Technology Inc., Hsinchu Science Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/06 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0441 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01); G11C 2216/10 (2013.01);
Abstract

The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.


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