The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8957516 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 17, 2015

Filed:

Apr. 07, 2014
Applicant:

Broadcom Corporation, Irvine, CA (US);

Inventors:

Mengzhi Pang, Cupertino, CA (US);

Ken Zhonghua Wu, Fremont, CA (US);

Matthew Kaufmann, Morgan Hill, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01); H01L 23/12 (2006.01); H01L 23/48 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/34 (2013.01); H01L 21/78 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 23/3675 (2013.01); H01L 23/5389 (2013.01); H01L 24/83 (2013.01); H01L 24/97 (2013.01); H01L 23/12 (2013.01); H01L 23/481 (2013.01); H01L 23/3121 (2013.01); H01L 2224/04105 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/97 (2013.01); H01L 2924/15153 (2013.01);
Abstract

A low cost and high performance flip chip package is disclosed. By assembling the package using a substrate panel level process, a separate fabrication of a substrate is avoided, thus enabling the use of a coreless substrate. The coreless substrate may include multiple stacked layers of laminate dielectric films having conductive traces and vias. As a result, electrical connection routes may be provided directly from die contact pads to package contact pads without the use of conventional solder bumps, thus accommodating very high density semiconductor dies with small feature sizes. The disclosed flip chip package provides lower cost, higher electrical performance, and improved thermal dissipation compared to conventional fabricated substrates with solder bumped semiconductor dies.


Find Patent Forward Citations

Pang, Mengzhi. (2015). Low cost and high performance flip chip package (U.S. Patent No. 8957516). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8957516

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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