The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 2015
Filed:
Mar. 09, 2012
Kazuaki Takesako, Taichung, TW;
Wen-kuei Hsu, Taichung, TW;
Yoshinori Tanaka, Taichung, TW;
Yukihiro Nagai, Taichung, TW;
Chih-wei Hsiung, Taichung, TW;
Hirotake Fujita, Taichung, TW;
Tomohiro Kadoya, Taichung, TW;
Wei-chih Liu, Taichung, TW;
Hsuan-yu Fang, Taichung, TW;
Yu-ling Huang, Taichung, TW;
Meng-hsien Chen, Taichung, TW;
Chun-chiao Tseng, Taichung, TW;
Chung-yung Ai, Taichung, TW;
Yu-shan Hsu, Taichung, TW;
Wei-che Chang, Taichung, TW;
Chun-hua Huang, Taichung, TW;
Kazuaki Takesako, Taichung, TW;
Wen-Kuei Hsu, Taichung, TW;
Yoshinori Tanaka, Taichung, TW;
Yukihiro Nagai, Taichung, TW;
Chih-Wei Hsiung, Taichung, TW;
Hirotake Fujita, Taichung, TW;
Tomohiro Kadoya, Taichung, TW;
Wei-Chih Liu, Taichung, TW;
Hsuan-Yu Fang, Taichung, TW;
Yu-Ling Huang, Taichung, TW;
Meng-Hsien Chen, Taichung, TW;
Chun-Chiao Tseng, Taichung, TW;
Chung-Yung Ai, Taichung, TW;
Yu-Shan Hsu, Taichung, TW;
Wei-Che Chang, Taichung, TW;
Chun-Hua Huang, Taichung, TW;
Rexchip Electronics Corporation, Taichung, TW;
Abstract
A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.