The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2015

Filed:

Nov. 06, 2013
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventors:

Tsung-Yuan Chen, Taoyuan County, TW;

Shih-Lian Cheng, Taoyuan County, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01R 9/00 (2006.01); H05K 3/40 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H05K 3/46 (2006.01); H05K 3/10 (2006.01); H01L 23/00 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4038 (2013.01); H01L 23/49822 (2013.01); H01L 21/4857 (2013.01); H05K 3/4694 (2013.01); H05K 3/10 (2013.01); H01L 2924/15311 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/83102 (2013.01); H01L 2224/131 (2013.01); H05K 3/3436 (2013.01); H05K 3/4644 (2013.01); H01L 2224/16225 (2013.01);
Abstract

A package substrate includes a core layer, a first dielectric layer, a second circuit pattern, a first solder mask and an insulating layer. A first circuit pattern is disposed on a first surface of the core layer. The first dielectric layer covers the first circuit pattern. The second circuit pattern is located on the first dielectric layer and the second circuit pattern includes an interconnection circuit pattern within a chip mounting area. The first solder mask covers a portion of the second circuit pattern outside the chip mounting area. The insulating layer covers the chip mounting area and the interconnection circuit pattern. A plurality of embedded pads are located on an upper surface of the insulating layer.


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