The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2015
Filed:
Dec. 31, 2011
Applicants:
Inder M. Sodhi, Folsom, CA (US);
Amjad M. Khan, Folsom, CA (US);
Zeev Offen, Folsom, CA (US);
Ryan D. Wells, Folsom, CA (US);
Inventors:
Inder M. Sodhi, Folsom, CA (US);
Amjad M. Khan, Folsom, CA (US);
Zeev Offen, Folsom, CA (US);
Ryan D. Wells, Folsom, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01);
Abstract
I/O logic can be separated into critical and non-critical portions, with the non-critical portions being powered down during processor idle. The I/O logic is separated into gate logic and ungated logic, where the ungated logic continues to be powered during a processor deep sleep state, and the gated logic is powered off during the deep sleep state. A power control unit can trigger the shutting down of the I/O logic.