The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2015

Filed:

Jan. 13, 2012
Applicants:

Daisuke Sasaki, Fujisawa, JP;

Masatoshi Hasegawa, Hachioji, JP;

Masahiko Nishiyama, Fujisawa, JP;

Testuya Fukuoka, Tachikawa, JP;

Inventors:

Daisuke Sasaki, Fujisawa, JP;

Masatoshi Hasegawa, Hachioji, JP;

Masahiko Nishiyama, Fujisawa, JP;

Testuya Fukuoka, Tachikawa, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01); H03K 19/00 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0016 (2013.01); H03K 17/687 (2013.01); H03K 19/00361 (2013.01);
Abstract

A semiconductor device that makes isolation circuits unnecessary and that also resolves the problem of through-current flowing during power supply shutdown transitions and during power supply recovery and that even flows between the regions during power shutdown. A semiconductor device of the present invention including a first power supply line, and a second power supply line coupled to a first power supply line by way of a first switch, a macro cell containing a macro cell core coupled to the second power supply line, and a third power supply line coupled by way of a second switch to a first power supply line, and a circuit block coupled to the third power supply line and also coupled to at least either the macro cell core input or output; and the second power supply line is coupled to the third power supply line.


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