The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2015

Filed:

Aug. 20, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Fung Ka Hing, Hsinchu, TW;

Haiting Wang, Hsinchu, TW;

Han-Ting Tsai, Kaohsiung, TW;

Chun-Fai Cheng, Hsinchu, TW;

Wei-Yuan Lu, Taipei, TW;

Hsien-Ching Lo, Taoyuan, TW;

Kuan-Chung Chen, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/3205 (2006.01); H01L 29/78 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7833 (2013.01); H01L 29/7834 (2013.01); H01L 21/76834 (2013.01); H01L 29/517 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/7836 (2013.01);
Abstract

A gate structure includes a gate dielectric over a substrate, and a gate electrode over the gate dielectric, wherein the gate dielectric contacts sidewalls of the gate electrode. The gate structure further includes a nitrogen-containing dielectric layer surrounding the gate electrode, and a contact etch stop layer (CESL) surrounding the nitrogen-containing dielectric layer. The gate structure further includes an interlayer dielectric layer surrounding the CESL and a lightly doped region in the substrate, the lightly doped region extends beyond an interface of the sidewalls of the gate electrode and the gate dielectric.


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