The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2015

Filed:

May. 16, 2013
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Kiwamu Sakuma, Yokohama, JP;

Haruka Kusai, Yokohama, JP;

Yasuhito Yoshimizu, Yokkaichi, JP;

Masahiro Kiyotoshi, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11551 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7881 (2013.01); H01L 29/792 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11565 (2013.01); H01L 27/1157 (2013.01); H01L 27/11578 (2013.01); H01L 29/42332 (2013.01); H01L 29/42348 (2013.01);
Abstract

According to one embodiment, a device includes a first fin structure having first to n-th semiconductor layers (n is a natural number equal to or more than 2) stacked in a first direction perpendicular to a surface of a semiconductor substrate, and extending in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory cells provided on surfaces of the first to n-th semiconductor layers in a third direction perpendicular to the first and second directions respectively, and first to n-th select transistors connected in series to the first to n-th memory cells respectively.


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