The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2015
Filed:
Oct. 25, 2013
Samsung Electro-mechanics Co., Ltd., Suwon, KR;
Sungkyunkwan University Foundation for Corporate Collaboration, Suwon, KR;
Seung Wook Park, Suwon, KR;
Young Do Kweon, Seoul, KR;
Jang Hyun Kim, Suwon, KR;
Tae Seok Park, Suwon, KR;
Su Jeong Suh, Suwon, KR;
Jae Gwon Jang, Goheung, KR;
Nam Jung Kim, Suwon, KR;
Seung Kyu Lim, Uiwang, KR;
Kwang Keun Lee, Wonju, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Sungkyunkwan University Foundation for Corporate Collaboration, Suwon, KR;
Abstract
A method of fabricating a package substrate, includes forming a cavity in at least one region of an upper surface of a wafer, the cavity including a chip mounting region, forming a through-hole penetrating through the wafer and a via filling the through-hole, forming a first wiring layer and a second wiring layer spaced apart from the first wiring layer, which are extended into the cavity, and mounting a chip in the cavity to be connected to the first wiring layer and the second wiring layer.