The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2015

Filed:

Jul. 11, 2011
Applicants:

Wei-sheng Lei, San Jose, CA (US);

Brad Eaton, Menlo Park, CA (US);

Madhava Rao Yalamanchili, Morgan Hill, CA (US);

Saravjeet Singh, Santa Clara, CA (US);

Ajay Kumar, Cupertino, CA (US);

Aparna Iyer, Sunnyvale, CA (US);

Inventors:

Wei-Sheng Lei, San Jose, CA (US);

Brad Eaton, Menlo Park, CA (US);

Madhava Rao Yalamanchili, Morgan Hill, CA (US);

Saravjeet Singh, Santa Clara, CA (US);

Ajay Kumar, Cupertino, CA (US);

Aparna Iyer, Sunnyvale, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); B23K 26/00 (2014.01); H01L 21/3065 (2006.01); H01L 21/78 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3065 (2013.01); H01L 21/78 (2013.01); B23K 26/00 (2013.01); H01L 21/67207 (2013.01);
Abstract

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a split-beam laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.


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