The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2015
Filed:
Aug. 06, 2009
Applicants:
Jozef C. Mitros, Richardson, TX (US);
Keith Jarreau, Plano, TX (US);
Pinghai Hao, Plano, TX (US);
Inventors:
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7883 (2013.01); H01L 29/0692 (2013.01); H01L 29/42324 (2013.01); H01L 29/66825 (2013.01); H01L 21/28273 (2013.01);
Abstract
A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.