The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2015
Filed:
Jun. 04, 2012
Oliver Haeberlen, Villach, AT;
Walter Rieger, Arnoldstein, AT;
Martin Vielemeyer, Villach, AT;
Lutz Goergens, Villach, AT;
Martin Poelzl, Ossiach, AT;
Milko Paolucci, Villach, AT;
Johannes Schoiswohl, San Jose, CA (US);
Sonja Krumrey, Goedersdorf, AT;
Oliver Haeberlen, Villach, AT;
Walter Rieger, Arnoldstein, AT;
Martin Vielemeyer, Villach, AT;
Lutz Goergens, Villach, AT;
Martin Poelzl, Ossiach, AT;
Milko Paolucci, Villach, AT;
Johannes Schoiswohl, San Jose, CA (US);
Joachim Krumrey, Goedersdorf, AT;
Infineon Technologies Austria AG, Villach, AT;
Abstract
A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.