The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8946033 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 03, 2015

Filed:

Jul. 30, 2012
Applicants:

Thomas N. Adam, Slingerlands, NY (US);

Keith E. Fogel, Hopewell Junction, NY (US);

Jinghong LI, Poughquag, NY (US);

Alexander Reznicek, Troy, NY (US);

Inventors:

Thomas N. Adam, Slingerlands, NY (US);

Keith E. Fogel, Hopewell Junction, NY (US);

Jinghong Li, Poughquag, NY (US);

Alexander Reznicek, Troy, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 29/66795 (2013.01);
Abstract

A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are () surfaces and the longitudinal axes of the two or more fins aligned with a [] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate.


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