The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2015
Filed:
Oct. 11, 2013
Cadence Design Systems, Inc., San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A system, method, and computer program product for automatically providing circuit designers with verification coverage information for analog/mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to assemble a schematic representation of a lower-level circuit design from pre-defined building blocks and various types of connections. Embodiments convert the schematic representation into a behavioral model for rapid simulation. Building blocks in the behavioral circuit have coverage-related terms defined either by the designer or by default, such as input and output value ranges, internal state changes, and state timers and timing-related constraints. Embodiments simulate the behavioral circuit, and determine and tangibly output coverage-related information. Manual and automatic behavioral circuit and stimulus modification can maximize coverage for improved behavioral circuit verification. Corresponding improvements to the underlying circuit may result, along with greatly reduced and better focused design and simulation efforts.